1. Field of the Invention
The present invention relates to a vertical PNP transistor and relative fabrication method.
2. Discussion of the Related Art
As is known, in integrated circuits, vertical PNP transistors (i.e. in which current flows vertically, crosswise to the surface of the wafer of semiconductor material in which the transistors are integrated) are frequently formed simultaneously with NPN transistors. As traditional methods, however, of fabricating integrated circuits comprising both types of transistors involve a good deal of time and expense, various solutions have been devised for reducing the fabrication steps required, described for example in European Patent N. 0 339 732 filed by SGS-THOMSON MICROELECTRONICS (corresponding to U.S. Pat. No. 4,898,836) and shown in FIG. 1.
As illustrated in FIG. 1, which shows a cross section of a semiconductor material wafer 1 with a top surface 2, the known solution referred to is based on the use of an N type substrate 4 on which an N type epitaxial layer 5 is grown; and separate P.sup.+ type buried regions 6, 7 are formed astride substrate 4 and epitaxial layer 5, and are connected to surface 2 by respective P.sup.+ type sinkers 8, 9 extending from the outer lateral edges of respective P.sup.+ type buried regions 6, 7 and externally defining respective epitaxial tubs 10, 11 for respectively housing an NPN transistor 12 and PNP transistor 13.
More specifically, P.sup.+ type buried region 6 constitutes an isolation region for electrically separating the NPN transistor from substrate 4 and epitaxial layer 5; an N.sup.+ type buried collector region 15 is formed inside buried isolation region 6 and projects slightly inside epitaxial tub 10; a low-resistivity N.sup.+ type region 14 and a detached P.sup.+ type base region 16 are formed inside tub 10 facing surface 2 of wafer 1; an N.sup.+ type emitter region 17 is formed inside base region 16 and facing surface 2; and NPN transistor 12 is completed by collector, base and emitter metal contact regions 20, 21, 22 formed through a protective oxide layer 18 and in direct electric contact with respective regions 14, 16, 17.
Together with P.sup.+ sinker 9 and a P type region 25 extending inside epitaxial tub 11, P.sup.+ type region 7 forms a collector region. More specifically, region 25 extends vertically from surface 2 of wafer 1 to buried collector region 7, and houses an N.sup.+ type base region 26 facing surface 2 of wafer 1; a low-resistivity N.sup.+ type region 27 and a detached P.sup.+ type emitter region 28 are formed inside base region 26 facing surface 2; and PNP transistor 13 is completed by collector, base and emitter metal contact regions 30, 31, 32 formed through protective oxide layer 18 in direct electric contact with respective regions 9, 27, 28.
The structure is completed by a low-resistivity N.sup.+ type region 33 formed in the epitaxial region outside sinkers 8, 9, facing surface 2, in direct contact with an isolation metal region 34 for biasing substrate 4.
Using the fabrication method described in the above patent, the FIG. 1 structure is formed by first simultaneously forming isolation sinker 8 of NPN transistor 12 and collector sinker 9 of PNP transistor 13; P type doping agents are then implanted and diffused with low concentration in epitaxial tub 11 to form region 25 and ensure electric continuity between base region 26 and sinker collector region 9; base region 26 and regions 27, 28 are then formed.
The above known method therefore requires specific steps for forming collector region 25 and base region 26, and, though reduced compared with former structures, still involves considerable fabrication cost in need of reduction.